projects / openwrt / openwrt.git / blob
? search:


110c6c6e473c389abfff84ad0af0c93465b41ec2
[openwrt/openwrt.git] /
1 From 172dc9a0d7704051c63407af6b39939c43801a99 Mon Sep 17 00:00:00 2001
2 From: Lei Wei <quic_leiwei@quicinc.com>
3 Date: Fri, 1 Mar 2024 13:36:26 +0800
4 Subject: [PATCH 34/50] net: ethernet: qualcomm: Add PPE port MAC address and
5 EEE functions
6
7 Add PPE port MAC address set and EEE set API functions which
8 will be used by netdev ops and ethtool.
9
10 Change-Id: Id2b3b06ae940b3b6f5227d927316329cdf3caeaa
11 Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
12 ---
13 drivers/net/ethernet/qualcomm/ppe/ppe_port.c | 75 ++++++++++++++++++++
14 drivers/net/ethernet/qualcomm/ppe/ppe_port.h | 3 +
15 drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 29 ++++++++
16 3 files changed, 107 insertions(+)
17
18 --- a/drivers/net/ethernet/qualcomm/ppe/ppe_port.c
19 +++ b/drivers/net/ethernet/qualcomm/ppe/ppe_port.c
20 @@ -462,6 +462,81 @@ void ppe_port_get_stats64(struct ppe_por
21 }
22 }
23
24 +/**
25 + * ppe_port_set_mac_address() - Set PPE port MAC address
26 + * @ppe_port: PPE port
27 + * @addr: MAC address
28 + *
29 + * Description: Set MAC address for the given PPE port.
30 + *
31 + * Return: 0 upon success or a negative error upon failure.
32 + */
33 +int ppe_port_set_mac_address(struct ppe_port *ppe_port, const u8 *addr)
34 +{
35 + struct ppe_device *ppe_dev = ppe_port->ppe_dev;
36 + int port = ppe_port->port_id;
37 + u32 reg, val;
38 + int ret;
39 +
40 + if (ppe_port->mac_type == PPE_MAC_TYPE_GMAC) {
41 + reg = PPE_PORT_GMAC_ADDR(port);
42 + val = (addr[5] << 8) | addr[4];
43 + ret = regmap_write(ppe_dev->regmap, reg + GMAC_GOL_ADDR0_ADDR, val);
44 + if (ret)
45 + return ret;
46 +
47 + val = (addr[0] << 24) | (addr[1] << 16) |
48 + (addr[2] << 8) | addr[3];
49 + ret = regmap_write(ppe_dev->regmap, reg + GMAC_GOL_ADDR1_ADDR, val);
50 + if (ret)
51 + return ret;
52 + } else {
53 + reg = PPE_PORT_XGMAC_ADDR(port);
54 + val = (addr[5] << 8) | addr[4] | XGMAC_ADDR_EN;
55 + ret = regmap_write(ppe_dev->regmap, reg + XGMAC_ADDR0_H_ADDR, val);
56 + if (ret)
57 + return ret;
58 +
59 + val = (addr[3] << 24) | (addr[2] << 16) |
60 + (addr[1] << 8) | addr[0];
61 + ret = regmap_write(ppe_dev->regmap, reg + XGMAC_ADDR0_L_ADDR, val);
62 + if (ret)
63 + return ret;
64 + }
65 +
66 + return 0;
67 +}
68 +
69 +/**
70 + * ppe_port_set_mac_eee() - Set EEE configuration for PPE port MAC
71 + * @ppe_port: PPE port
72 + * @eee: EEE settings
73 + *
74 + * Description: Set port MAC EEE settings for the given PPE port.
75 + *
76 + * Return: 0 upon success or a negative error upon failure.
77 + */
78 +int ppe_port_set_mac_eee(struct ppe_port *ppe_port, struct ethtool_eee *eee)
79 +{
80 + struct ppe_device *ppe_dev = ppe_port->ppe_dev;
81 + int port = ppe_port->port_id;
82 + u32 val;
83 + int ret;
84 +
85 + ret = regmap_read(ppe_dev->regmap, PPE_LPI_EN_ADDR, &val);
86 + if (ret)
87 + return ret;
88 +
89 + if (eee->tx_lpi_enabled)
90 + val |= PPE_LPI_PORT_EN(port);
91 + else
92 + val &= ~PPE_LPI_PORT_EN(port);
93 +
94 + ret = regmap_write(ppe_dev->regmap, PPE_LPI_EN_ADDR, val);
95 +
96 + return ret;
97 +}
98 +
99 /* PPE port and MAC reset */
100 static int ppe_port_mac_reset(struct ppe_port *ppe_port)
101 {
102 --- a/drivers/net/ethernet/qualcomm/ppe/ppe_port.h
103 +++ b/drivers/net/ethernet/qualcomm/ppe/ppe_port.h
104 @@ -8,6 +8,7 @@
105
106 #include <linux/phylink.h>
107
108 +struct ethtool_eee;
109 struct rtnl_link_stats64;
110
111 /**
112 @@ -86,4 +87,6 @@ void ppe_port_get_strings(struct ppe_por
113 void ppe_port_get_ethtool_stats(struct ppe_port *ppe_port, u64 *data);
114 void ppe_port_get_stats64(struct ppe_port *ppe_port,
115 struct rtnl_link_stats64 *s);
116 +int ppe_port_set_mac_address(struct ppe_port *ppe_port, const u8 *addr);
117 +int ppe_port_set_mac_eee(struct ppe_port *ppe_port, struct ethtool_eee *eee);
118 #endif
119 --- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
120 +++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
121 @@ -18,6 +18,16 @@
122 #define PPE_PORT5_SEL_PCS1 BIT(4)
123 #define PPE_PORT_SEL_XGMAC(x) (BIT(8) << ((x) - 1))
124
125 +/* PPE port LPI enable register */
126 +#define PPE_LPI_EN_ADDR 0x400
127 +#define PPE_LPI_PORT1_EN BIT(0)
128 +#define PPE_LPI_PORT2_EN BIT(1)
129 +#define PPE_LPI_PORT3_EN BIT(2)
130 +#define PPE_LPI_PORT4_EN BIT(3)
131 +#define PPE_LPI_PORT5_EN BIT(4)
132 +#define PPE_LPI_PORT6_EN BIT(5)
133 +#define PPE_LPI_PORT_EN(x) (BIT(0) << ((x) - 1))
134 +
135 /* There are 15 BM ports and 4 BM groups supported by PPE,
136 * BM port (0-7) is matched to EDMA port 0, BM port (8-13) is matched
137 * to PPE physical port 1-6, BM port 14 is matched to EIP.
138 @@ -580,6 +590,17 @@
139 #define GMAC_SPEED_100 1
140 #define GMAC_SPEED_1000 2
141
142 +/* GMAC MAC address register */
143 +#define GMAC_GOL_ADDR0_ADDR 0x8
144 +#define GMAC_ADDR_BYTE5 GENMASK(15, 8)
145 +#define GMAC_ADDR_BYTE4 GENMASK(7, 0)
146 +
147 +#define GMAC_GOL_ADDR1_ADDR 0xC
148 +#define GMAC_ADDR_BYTE0 GENMASK(31, 24)
149 +#define GMAC_ADDR_BYTE1 GENMASK(23, 16)
150 +#define GMAC_ADDR_BYTE2 GENMASK(15, 8)
151 +#define GMAC_ADDR_BYTE3 GENMASK(7, 0)
152 +
153 /* GMAC control register */
154 #define GMAC_CTRL_ADDR 0x18
155 #define GMAC_TX_THD_M GENMASK(27, 24)
156 @@ -705,6 +726,14 @@
157 #define XGMAC_RX_FLOW_CTRL_ADDR 0x90
158 #define XGMAC_RXFCEN BIT(0)
159
160 +/* XGMAC MAC address register */
161 +#define XGMAC_ADDR0_H_ADDR 0x300
162 +#define XGMAC_ADDR_EN BIT(31)
163 +#define XGMAC_ADDRH GENMASK(15, 0)
164 +
165 +#define XGMAC_ADDR0_L_ADDR 0x304
166 +#define XGMAC_ADDRL GENMASK(31, 0)
167 +
168 /* XGMAC management counters control register */
169 #define XGMAC_MMC_CTRL_ADDR 0x800
170 #define XGMAC_MCF BIT(3)
OpenWrt Source Repository